1. Field of the Invention
The present invention relates to transistors, transistor array panels having a matrix array of the transistors, and active-matrix displays using the transistor array panels. The present invention further relates to methods for driving the active-matrix display.
2. Description of the Related Art
The need for flat-panel displays of low power consumption is increasing with the development of information equipment, and the research and development of displays which meet this need is being actively conducted. In particular, wearable PCs and electronic personal organizers are often intended to be used out of doors and consequently power-thrifty and space-saving models are desired. A liquid-crystal display is one of such desirable displays.
Most liquid crystals used in liquid-crystal displays do not have a memory function for retaining the state of the display when its power is turned off. Therefore, the liquid crystals are necessarily supplied with voltage for the duration of display. On the other hand, it is difficult to secure the reliability of liquid crystals having a memory function when they are applied to wearable PCs or the like which are supposed to be used in various environments. Recently, such liquid crystals have been gradually put to practical use, but they still have many problems.
An electrophoretic display disclosed in U.S. Pat. No. 3,612,758 is an example of a lightweight flat display having a memory function. That display includes a pair of substrates disposed so as to have a predetermined gap therebetween; an insulating liquid filled between the substrates; a large number of colored charged electrophoretic particles dispersed in the insulating liquid; and display electrodes disposed in each pixel so as to be along the substrates.
In this display, since the colored charged electrophoretic particles are positively or negatively charged, the particles are adsorbed on display electrodes depending on the polarity of the voltage applied to the display electrodes. In the state that the colored particles are adsorbed on the top electrodes, the colored particles are seen; and in the state that the colored particles are adsorbed on the bottom electrodes, the insulating liquid is seen. The state can be controlled by adjusting an applied voltage. Thus, various images can be displayed. Such a display is known as a “vertical-movement-type” display.
Another example of the electrophoretic display is disclosed in Japanese Patent Laid-Open No. 9-211499. FIGS. 7A and 7B are cross-sectional views illustrating the structure of this electrophoretic display, wherein a pixel is composed of a first substrate 31 and a second substrate 32 disposed so as to oppose each other, and spacers 33 for maintaining a predetermined distance between these two substrates. In the space defined by the substrates and the spacers, an insulating fluid 34 and black electrophoretic particles 35 are encapsulated. The insulating liquid 34 is transparent.
The second substrate 32 is provided with a first electrode 36 and second electrodes 37 for driving a display device, and an insulating film 38 covers them. The first electrode 36 is disposed over the entire pixel and also serves as a reflective layer for reflecting incident light. The second electrodes 37 are disposed along the spacers 33 and may be colored black so as to also serve as a light-shielding layer.
FIGS. 7A and 7B show the pixel in two different states of displays.
FIG. 7A shows the pixel in the state when a voltage of a polarity opposite to that of the electrophoretic particles 35 is applied to the first electrode 36 and a voltage of a polarity identical to that of the electrophoretic particles 35 is applied to the second electrodes 37. The electrophoretic particles 35 are drawn toward the first electrode 36 to cover the top face thereof and the pixel is displayed in black. This state is converted to the state shown in FIG. 7B by inverting the polarities of the first electrode 36 and the second electrodes 37. The electrophoretic particles 35 are drawn toward the second electrodes 37 and the pixel is displayed as white. Thus, an image is displayed by controlling the polarity and amplitude of the voltage applied to the electrodes for each pixel.
In order to drive the electrophoretic display, the display devices constituting the pixel are each provided with a thin-film transistor (TFT) to form an active matrix array (simply referred to as TFT array). The TFT active matrix array is disposed in or under the second substrate 32 shown in FIGS. 7A and 7B.
The TFT may have various structures such as a bottom-gate TFT structure, which has a gate electrode disposed below an active layer on which a channel is formed; a top-gate TFT structure; and a plate TFT structure.
FIG. 8 is a cross-sectional view illustrating the bottom-gate TFT structure.
The TFT includes a gate electrode 12 on a glass substrate 10; a gate insulating film 14 on the gate electrode 12; an amorphous semiconductor layer 15 on the gate insulating film 14; and a source electrode 16 and a drain electrode 17 connected through the ohmic contact layer 19 disposed on the amorphous semiconductor layer 15. Additionally, a channel protective film 18 for covering the exposed face of the amorphous semiconductor layer 15 is disposed on the source electrode 16 and the drain electrode 17.
The display device shown in FIGS. 7A and 7B is provided on the TFT (not shown in FIG. 8). The first electrode 36 or the second electrode 37 is connected to the drain electrode via a contact hole provided in the channel protective film 18. Another electrode which is not connected to the drain electrode is set at a common electric potential.
In the right area of FIG. 8, a cross-section of a storage capacitor is drawn. The storage capacitor is provided for retaining the voltage of the display device.
A storage capacitor (Cs) electrode 13 is disposed on the substrate 10; and on the storage capacitor electrode 13, a gate insulating film 14, an amorphous semiconductor layer 15, an ohmic contact layer 19, and a drain electrode 17 are laminated. The drain electrode 17 and the storage capacitor electrode 13 as a counter electrode constitute a capacitor, i.e., a storage capacitor by interposing the ohmic contact layer 19, the amorphous semiconductor layer 15, and the gate insulating film 14 therebetween.
The storage capacitor may not have the ohmic contact layer 19 and the amorphous semiconductor layer 15, that is, the storage capacitor may be produced by sandwiching only the gate insulating film 14 between the drain electrode 17 and the storage capacitor electrode 13.
FIG. 9 is a layout plan view of a TFT and a display device. The horizontal direction in the drawing is set as an X-direction and the vertical direction is set as a Y-direction.
Patterns of a gate electrode 12 and a storage capacitor electrode 13 are formed in the same layer on a glass substrate 10 with the same material. On the patterns, a gate insulating film (not shown) is formed to cover the whole area, and an amorphous semiconductor layer 15a (15b) having the same pattern as that of an ohmic contact layer (not shown) is further formed. On the amorphous semiconductor layer 15a (15b), through the ohmic contact layer 19, patterns of a source electrode 16a (16b) and a drain electrode 17a (17b) are formed in the same layer with the same material.
Furthermore, a channel protective film 18 is formed on the whole area, and a pixel electrode 20 is formed thereon. Here, the first electrode 36 disposed over the entire pixel in FIGS. 7A and 7B corresponds to a pixel electrode 20.
The drain electrode 17a (17b) is formed as a rectangular pattern on the storage capacitor electrode 13 to constitute a storage capacitor. The contact of the drain electrode 17a (17b) with the pixel electrode 20 is not shown, but the drain electrode 17a (17b) is in contact with the pixel electrode 20 via a contact hole formed in the channel protective film 18 disposed on the drain electrode.
The amorphous semiconductor layer 15b, the source electrode 16b, and the drain electrode 17b belong to the TFT of the adjacent pixel. If the amorphous semiconductor layers 15a and 15b of the adjacent pixels are connected to each other to form a band between the TFT, the electrode potential of the drain electrode 17a is affected by the source electrode 16b. In order to avoid this, the patterns of the amorphous semiconductor layers 15a and 15b are disconnected from each other.
The source electrode 16a (16b) extends in the Y-direction and is connected to other TFTs at the top and the bottom thereof. The drain electrodes 17a and 17b are opposite to the source electrodes 16a and 16b, respectively. A portion where the amorphous semiconductor layer lies between the opposing drain electrode 17a and source electrode 16a is called a channel hereinafter. Since a gate electrode is disposed under the amorphous semiconductor layer of the channel through a gate insulating film, the electrical conductivity of the channel, i.e., voltage-current characteristic between the source and the drain electrodes, is controlled by the potential of the gate electrode.
In this specification, the width of a portion where the amorphous semiconductor layer 15a (15b) lies is referred to as the channel width and the distance between the opposing drain electrode and source electrode so as to have the channel therebetween is referred to as the channel length.
In FIG. 9, the drain electrode 17a (17b) is formed with a pattern different from those of the amorphous semiconductor layer 15a (15b) and the ohmic contact layer 19. However, the drain electrode may be formed with the same pattern as that of the amorphous semiconductor layer 15a (15b) and the ohmic contact layer 19 by laminating three layers of the amorphous semiconductor layer, ohmic contact layer, and drain electrode and then performing a photolithography process for one mask. In such a case, the amorphous semiconductor layer 15a is formed not only at the portion shown by a broken line in FIG. 9 but also under the source electrode 16a (16b) and the drain electrode 17a (17b).
As shown in FIG. 9, the pattern of the amorphous semiconductor layer 15a (15b) is formed within the region of the gate electrode 12 so as to be smaller than that of the gate electrode 12. This provides an allowance (hereinafter referred to as a margin) for displacement of the amorphous semiconductor layer 15a (15b).
In FIG. 9, the reference character Ma denotes a margin for displacement of the amorphous semiconductor layer 15a in the Y-direction and the reference character Mb denotes a margin for displacement of the amorphous semiconductor layer 15a in the X-direction.
If the pattern of the amorphous semiconductor layer 15a is shifted more than ±Mb in the X-direction, the contact area of the amorphous semiconductor layer 15a with the source electrode or the drain electrode is decreased; which causes an increase in the resistance between the source and drain electrodes.
If the pattern of the amorphous semiconductor layer 15a is shifted more than ±Ma in the Y-direction, the pattern of the amorphous semiconductor 15a lies outside the gate electrode 12; which causes not only a decrease in the channel width which can be controlled by adjusting the gate voltage but also an increase in the leakage current of the TFT by the occurrence of an uncontrollable semiconductor region in the channel. As a result, a desired voltage-current characteristic cannot be achieved.
These margins for the displacement are allowances for error in placement of patterns in lithography and etching processes. The margin is determined in consideration of the positioning accuracy between the amorphous semiconductor layer and a photomask in a lithography process of forming the amorphous semiconductor layer and the degree of expansion/contraction of the substrate caused by a heating process.
As long as the displacement is within the margin, the width (W) and the length (L) of the channel-forming area on the TFT and the ratio (W/L) are not changed. Therefore, the voltage-current characteristic of the TFT is constant.
Recently, a display using an electrophoretic device is adopted instead of paper. The display is thin and heavy duty. Since the display is treated as a piece of paper, a technology for forming a TFT array on a thin metal or plastic substrate instead of the existing glass substrate is desired.
One reason for using the metal substrate is that it is resistant to heating in a TFT-manufacturing process. Another reason is that a metal substrate in the form of a thin foil can be inserted into a narrow container by being rolled up as a sheet of paper; which enhances the convenience of a display using the substrate.
Japanese Patent Laid-Open No. 9-179106 discloses a TFT array formed on a metal substrate, in particular, a stainless steel substrate such as SUS420 (hereinafter abbreviated as SUS).
However, since the coefficient of linear expansion of SUS is higher than that of glass, it is difficult to form a TFT array having high-resolution patterns.
The coefficient (α) of linear expansion of SUS is higher than twice the coefficient of glass (α=3×10−6/K to 5×10−6/K: glass with a low coefficient of linear expansion). Therefore, since the size of the SUS substrate is largely changed by the heating and cooling during the manufacture process, the margin for displacement must be broad. As a result, the area necessary for the formation of the TFT becomes large. Therefore, it is difficult to produce a display with high resolution. Additionally, the storage capacitor is decreased and the parasitic capacitor is increased; which are problems.